SH7706 Datasheet, PDF (196/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
Bit
Bit Name Initial Value R/W Description
15
SCMFCA 0
R/W CPU Condition Match Flag A
When the CPU bus cycle condition in the break
conditions set for channel A is satisfied, this flag
is set to 1 (not cleared to 0). In order to clear this
flag, write 0 into this bit.
0: The CPU cycle condition for channel A does
not match
1: The CPU cycle condition for channel A
matches
14
SCMFCB 0
R/W CPU Condition Match Flag B
When the CPU bus cycle condition in the break
conditions set for channel B is satisfied, this flag
is set to 1 (not cleared to 0). In order to clear this
flag, write 0 into this bit.
0: The CPU cycle condition for channel B does
not match
1: The CPU cycle condition for channel B
matches
13
SCMFDA 0
R/W DMAC Condition Match Flag A
When the on-chip DMAC bus cycle condition in
the break conditions set for channel A is
satisfied, this flag is set to 1 (not cleared to 0). In
order to clear this flag, write 0 into this bit.
0: The DMAC cycle condition for channel A does
not match
1: The DMAC cycle condition for channel A
matches
12
SCMFDB 0
R/W DMAC Condition Match Flag B
When the on-chip DMAC bus cycle condition in
the break conditions set for channel B is
satisfied, this flag is set to 1 (not cleared to 0). In
order to clear this flag, write 0 into this bit.
0: The DMAC cycle condition for channel B does
not match
1: The DMAC cycle condition for channel B
matches
Rev. 5.00 May 29, 2006 page 148 of 698
REJ09B0146-0500