SH7706 Datasheet, PDF (181/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

6.5 Operation
Section 6 Interrupt Controller (INTC)
6.5.1 Interrupt Sequence
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt from the interrupt requests sent,
following the priority levels set in interrupt priority registers A to E (IPRA to IPRE). Lower
priority interrupts are held pending. If two of these interrupts have the same priority level or if
multiple interrupts occur within a single module, the interrupt with the highest default priority
or the highest priority within its IPR setting unit (as indicated in table 6.3 and table 6.4) is
selected.
3. The priority level of the interrupt selected by the interrupt controller is compared with the
interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level
is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU. When the interrupt controller receives an interrupt, a
low level is output from the IRQOUT pin.
4. Detection timing: The INTC operates in synchronization with the peripheral clock (Pφ), and
reports the interrupt request to the CPU. The CPU receives an interrupt at a break in
instruction.
5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2).
6. The SR and PC are saved to SSR and SPC, respectively.
7. The BL, MD, and RB in SR are set to 1.
8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the
vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt
handler may branch with the INTEVT register value as its offset in order to identify the
interrupt source. This enables it to branch to the processing routine for the individual interrupt
source.
Notes: 1. The interrupt mask bits (I3 to I0) in the SR are not changed by acceptance of an
interrupt in this LSI.
2. IRQOUT outputs a low level until the interrupt request is cleared. However, if the
interrupt source is masked by an interrupt mask bit, the IRQOUT pin returns to the
high level. The level is output without regard to the BL bit.
3. The interrupt source flag should be cleared in the interrupt handler. The interrupt
source flag should be cleared in the interrupt handler. To ensure that an interrupt
request that should have been cleared is not inadvertently accepted again, read the
Rev. 5.00 May 29, 2006 page 133 of 698
REJ09B0146-0500