SH7706 Datasheet, PDF (426/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
4
FER
0
R/(W)* Framing Error
Indicates that data reception aborted due to a framing
error in the asynchronous mode.
0: Receiving is in progress or has ended normally
[Clearing conditions]
1. The chip is reset or enters standby mode.
2. FER is read as 1, then written to with 0.
Note: Clearing the RE bit to 0 in the serial control
register does not affect the FER bit, which retains
its previous value.
1: A receive framing error occurred
[Setting condition]
When the SCI has completed receiving, the stop bit
at the end of receive data is checked and found to
be 0.
Note: When the stop bit length is two bits, only the
first bit is checked. The second stop bit is not
checked. When a framing error occurs, the SCI
transfers the receive data into the SCRDR but does
not set RDRF. Serial receiving cannot continue
while FER is set to 1. In the clock synchronous
mode, serial transmitting is also disabled.
Rev. 5.00 May 29, 2006 page 378 of 698
REJ09B0146-0500