SH7706 Datasheet, PDF (625/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 22 Power-Down Modes
Bit
Value Description
MSTP8 0
UBC runs.
1
Supply of clock to UBC halted.
MSTP7 0
DMAC runs.
1
Supply of clock to DMAC halted.
MSTP6 0
DAC runs.
1
Supply of clock to DAC halted.
MSTP5 0
ADC runs.
1
Supply of clock to ADC halted, and all registers initialized.
MSTP4 0
SCIF runs.
1
Supply of clock to SCIF halted.
MSTP2 0
1
TMU runs.
Supply of clock to TMU halted. Registers initialized.^*1
MSTP1 0
1
RTC runs.
Supply of clock to RTC halted. Register access prohibited.^*2
MSTP0 0
SCI runs.
1
Supply of clock to SCI halted.
Notes: 1. The registers initialized are the same as in the software standby mode (table 22.3).
2. The counter runs.
Clearing the Module Standby Function
The module standby function can be cleared by clearing the MSTP8 to MSTP4, MSTP2 to
MSTP0 bits to 0, or by a power-on reset or manual reset.
Rev. 5.00 May 29, 2006 page 577 of 698
REJ09B0146-0500