SH7706 Datasheet, PDF (455/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Receiving Multiprocessor Serial Data: Figure 14.15 shows a sample flowchart for receiving
multiprocessor serial data. Reception of multiprocessor serial data should be carried out in the
following procedure after setting the SCI in a reception-enabled state.
Start reception
Set MPIE bit in SCSCR to 1
Read ORER and FER
bits in SCSSR
FER = 1 or ORER = 1?
Yes
No
Read RDRF bit in SCSSR
No
RDRF = 1?
Yes
Read receive data in SCRDR
No
Is ID the
stations ID?
Yes
Read ORER and FER
bits in SSCSR
1. ID receive cycle: Set the MPIE
bit in SCSCR to 1.
2. SCI status check and compare
to ID reception: Read the SCSSR,
check that RDRF is set to 1, then
read data from the SCRDR and
compare with the processor's own
ID. If the ID does not match the
receive data, set MPIE to 1 again
and clear RDRF to 0. If the ID
matches the receive data, clear
RDRF to 0.
3. SCI status check and data receiving:
Read SCSSR, check that RDRF is
set to 1, then read data from the
SCRDR.
FER = 1 or ORER = 1?
Yes
No
Read RDRF bit in SCSSR
RDRF = 1?
No
Yes
Read receive data in SCRDR
4. Receive error processing and break
detection: If a receive error occurs,
read the ORER and FER bits in
SCSSR to identify the error. After
executing the necessary error
processing, clear both ORER and
FER to 0. Receiving cannot resume
if ORER or FER remain set to 1.
When a framing error occurs, the
RxD0 pin can be read to detect the
break state.
No
All data received?
Yes
Clear RE bit in SCSCR to 0
Error processing
End reception
Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data
Rev. 5.00 May 29, 2006 page 407 of 698
REJ09B0146-0500