SH7706 Datasheet, PDF (491/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
SCPT[3]/SCK2
Reset
R
D
SCP3MD0
Q
C
PCRW
Reset
R
QD
SCP3MD1
C
PCRW
Reset
R
QD
SCP3DT1
C
PDRW
Internal data bus
SCIF
Clock input enable
Output enable
Serial clock output
PDRR*
Serial clock input
Legend:
PDRW: SCPDR write
PDRR: SCPDR read
PCRW: SCPCR write
Note: * When reading the SCK2 pin, clear the CKE1 and CKE0
bits in SCSCR to 0, and set the SCP3MD1 bit in SCSPR to 1.
Figure 16.2 SCPT[3]/SCK2 Pin
Rev. 5.00 May 29, 2006 page 443 of 698
REJ09B0146-0500