SH7706 Datasheet, PDF (205/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
If the PID value is odd, instruction buffer indicates PID+2 buffer. However, these expressions
in this table are accounted for it. Therefore, the true branch source address is calculated with
BSA and PID values stored in BRSR.
3. The branch address before branch occurrence, IA, has different values due to some kinds of
branch.
a. Branch instruction
The branch instruction address
b. Interrupt
The last instruction executed before interrupt
The top address of interrupt routine is stored in BRDR.
4. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the
address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read
BRSR and BRDR in order, the queue only shifts after BRDR is read. When reading BRDR,
longword access should be used. Also, the PC trace has a trace pointer, which initially points
to the bottom of the queues. The first pair of branch addresses will be stored at the bottom of
the queues, then push up when next pairs come into the queues. The trace pointer will points to
the next branch address to be executed, unless it got push out of the queues. When the branch
address has been executed, the trace pointer will shift down to next pair of addresses, until it
reaches the bottom of the queues. After switching the PCTE bit (in BRCR) off and on, the
values in the queues are invalid. The read pointer stay at the position before PCTE is switched,
but the trace pointer restart at the bottom of the queues.
Rev. 5.00 May 29, 2006 page 157 of 698
REJ09B0146-0500