SH7706 Datasheet, PDF (481/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 15 Smart Card Interface
Table 15.7 Register Set Values and SCKφ Pin
Register Value
SCK Pin
Setting SMIF C/A CKE1 CKE0
1^*1
1
0
0
0
Output
Port
State
Determined by setting of port register
SCP1MD1 and SCP1MD0 bits
1
0
0
1
2^*2
1
1
0
0
SCK0 (serial clock) output state
Low output Low output state
1
1
0
1
3^*2
1
1
1
0
SCK0 (serial clock) output state
High output High output state
1
1
1
1
SCK0 (serial clock) output state
Notes: 1. The SCK0 output state changes as soon as the CKE0 bit is modified. The CKE1 bit
should be cleared to 0.
2. The clock duty remains constant despite stopping and starting of the clock by
modification of the CKE0 bit.
15.4.6 Data Transmission and Reception
Initialization: Initialize the SCI using the following procedure before sending or receiving data.
Initialization is also required for switching from transmit mode to receive mode or from receive
mode to transmit mode. Figure 15.5 shows an example of initialization process flowchart.
1. Clear TE and RE in SCSCR to 0.
2. Clear error flags FER/ERS, PER, and ORER to 0 in SCSSR.
3. Set the C/A bit, parity bit (O/E bit), and baud rate generator select bits (CKS1 and CKS0 bits)
in SCSMR. At this time also clear the CHR and MP bits to 0 and set the STOP and PE bits to
1.
4. Set the SMIF, SDIR, and SINV bits in SCSCMR. When the SMIF bit is set to 1, the TxD and
RxD pins both switch from ports to SCI pins and become high impedance.
5. Set the value corresponding to the bit rate in SCBRR.
6. Set the clock source select bits (CKE1 and CKE0 bits) in SCSCR. Clear the TIE, RIE, TE, RE,
MPIE, and TEIE bits to 0. When the CKE0 bit is set to 1, a clock is output from the SCKφ pin.
7. After waiting at least 1 bit, set the TIE, RIE, TE, and RE bits in SCSCR. Do not set the TE and
RE bits simultaneously unless performing self-diagnosis.
Rev. 5.00 May 29, 2006 page 433 of 698
REJ09B0146-0500