SH7706 Datasheet, PDF (79/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
Classification Types
Arithmetic
21
operations
Logic
6
operations
Shift
12
Operation
Code
MUL
MULS
MULU
NEG
NEGC
SUB
SUBC
SUBV
AND
NOT
OR
TAS
TST
XOR
ROTL
ROTR
ROTCL
ROTCR
SHAL
SHAR
SHLL
SHLLn
SHLR
SHLRn
SHAD
SHLD
Function
Double-precision multiplication
(32 × 32 bits)
Signed multiplication (16 × 16 bits)
Unsigned multiplication (16 × 16 bits)
Negation
Negation with borrow
Binary subtraction
Binary subtraction with borrow
Binary subtraction with underflow check
Logical AND
Bit inversion
Logical OR
Memory test and bit set
Logical AND and T bit set
Exclusive OR
One-bit left rotation
One-bit right rotation
One-bit left rotation with T bit
One-bit right rotation with T bit
One-bit arithmetic left shift
One-bit arithmetic right shift
One-bit logical left shift
n-bit logical left shift
One-bit logical right shift
n-bit logical right shift
Dynamic arithmetic shift
Dynamic logical shift
No. of
Instructions
33
14
16
Rev. 5.00 May 29, 2006 page 31 of 698
REJ09B0146-0500