SH7706 Datasheet, PDF (122/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
Figure 3.10 shows the flowchart for MMU exceptions.
No
TLB miss
exception
Start
SH = 0
No
and (MMUCR.SV = 0
or SR.MD = 0)?
VPNs match?
No
Yes
Yes
VPNs
and ASIDs
match?
Yes
User mode
V = 1?
Yes
User or
privileged?
No
TLB invalid
exception
Privileged mode
PR check
00/01
10
W
R/W?
R
11
W
R/W?
R
No
PR check
01/11
00/10
W
R/W?
W
R/W?
R
R
D = 1?
TLB protection
violation
exception
Yes
TLB protection
violation
Initial page
write
exception
No (noncacheable)
Memory
access
C = 1?
Yes (cacheable)
Cache
access
Figure 3.10 MMU Exception Generation Flowchart
Rev. 5.00 May 29, 2006 page 74 of 698
REJ09B0146-0500