SH7706 Datasheet, PDF (337/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
CK
Internal
address bus
SAR_2 DAR_2 SAR_2+2 DAR_2 SAR_2+4 DAR_2 SAR_2+6 DAR_2 SAR_2
Internal
data bus
SAR_2 data
SAR_2+2 data
SAR_2+4 data
SAR_2+6 data
First transfer of
channel 2
SAR_2 output
DAR_2 output
Second transfer
SAR_2+2 output
DAR_2 output
Third transfer
SAR_2+4 output
DAR_2 output
Fourth transfer Fifth transfer
SAR_2+6 output SAR_2 reload
DAR_2 output SAR_2 output
DAR_2 output
Figure 9.25 Timing Chart of Source Address Reload Function
Even if the transfer data size is 8, 16, or 32 bits, a reload function can be executed.
DMATCR_2, which specifies a transfer count, decrements 1 each time a transfer ends regardless
of whether a reload function is on or off. Consequently, be sure to specify the value multiple of
four in DMATCR_2 when the reload function is on. Specifying other values does not guarantee
the operation.
Though the counters that count transfers of four times for the reload function are reset by clearing
the DME bit in DMAOR or the DE bit in CHCR_2, by setting the transfer end flag (TE bit in
CHCR_2) by a DMAC address error, or by inputting NMI, besides by resets, the SAR_2, DAR_2,
DMATCR_2 registers are not reset. Therefore, if these sources are generated, the counters that are
initialized and are not initialized exist in the DMAC; malfunction will be caused by restarting the
DMAC in that state. Consequently, if these sources occur except for setting the TE bit during the
usage of the reload function, set SAR_2, DAR_2, and DMATCR_2 again.
Rev. 5.00 May 29, 2006 page 289 of 698
REJ09B0146-0500