SH7706 Datasheet, PDF (609/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

21.4 H-UDI Operations
Section 21 User Debugging Interface (H-UDI)
21.4.1 TAP Controller
Figure 21.2 shows the internal states of TAP controller. State transitions basically conform with
the JTAG standard.
1 Test-logic-reset
0
1
0 Run-test/idle
1
Select-DR-scan
0
1
Capture-DR
0
Shift-DR 0
1
1
Exit1-DR
0
Pause-DR 0
1
0
Exit2-DR
1
Update-DR
10
1
Select-IR-scan
0
1
Capture-IR
0
Shift-IR 0
1
1
Exit1-IR
0
Pause-IR 0
1
0
Exit2-IR
1
Update-IR
10
Figure 21.2 TAP Controller State Transitions
Note:
The transition condition is the TMS value on the rising edge of TCK. The TDI value is
sampled on the rising edge of TCK; shifting occurs on the falling edge of TCK. The TDO
value changes on the TCK falling edge. The TDO is at high impedance, except with shift-
DR (shift-SR) and shift-IR states. When TRST = 0, there is a transition to test-logic-reset
asynchronously with TCK.
Rev. 5.00 May 29, 2006 page 561 of 698
REJ09B0146-0500