SH7706 Datasheet, PDF (483/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 15 Smart Card Interface
This processing can be interrupted. When the TIE bit is set to 1 and interrupt requests are enabled,
a transmit-data-empty interrupt (TXI) will be requested when the TEND flag is set to 1 at the end
of the transmission. When the RIE bit is set to 1 and interrupt requests are enabled, a
communication error interrupt (ERI) will be requested when the ERS flag is set to 1 when an error
occurs in transmission. See Interrupt Operation below for more information.
Start
Initialize
Start transmission
No
FER/ERS = 0?
Yes
No
TEND = 1?
Yes
Write transmit data in SCTDR
and clear TDRE
flag in SCSSR to 0
No
All data transmitted?
Yes
No
FER/ERS = 0?
Yes
No
TEND = 1?
Yes
Clear TE bit in SCSCR to 0
Error processing
Error processing
End transmission
Figure 15.6 Transmission Flowchart
Serial Data Reception: The processing procedures in the smart card mode are the same as in
ordinary SCI processing. The reception processing flowchart is shown in figure 15.7.
Rev. 5.00 May 29, 2006 page 435 of 698
REJ09B0146-0500