SH7706 Datasheet, PDF (80/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
Classification Types
Branch
9
System
15
control
Total:
68
Operation
Code
BF
BT
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
CLRMAC
CLRT
CLRS
LDC
LDS
LDTLB
NOP
PREF
RTE
SETS
SETT
SLEEP
STC
STS
TRAPA
Function
Conditional branch, delayed conditional
branch (T = 0)
Conditional branch, delayed conditional
branch (T = 1)
Unconditional branch
Unconditional branch
Branch to subroutine procedure
Branch to subroutine procedure
Unconditional branch
Branch to subroutine procedure
Return from subroutine procedure
MAC register clear
Clear T bit
Clear S bit
Load to control register
Load to system register
Load PTE to TLB
No operation
Prefetch data to cache
Return from exception handling
Set S bit
Set T bit
Shift to power-down mode
Store from control register
Store from system register
Trap exception handling
No. of
Instructions
11
75
188
The instruction codes are listed from tables 2.5 to 2.10. Those tables are described according to the
following items.
Rev. 5.00 May 29, 2006 page 32 of 698
REJ09B0146-0500