SH7706 Datasheet, PDF (192/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
7.2.4 Break Address Register B (BARB)
BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in
channel B.
Bit
31 to 0
Bit Name
BAB31 to
BAB0
Initial Value R/W
All 0
R/W
Description
Break Address
Stores the address of LAB or IAB that specifies
the break conditions of channel B.
7.2.5 Break Address Mask Register B (BAMRB)
BAMRB is a 32-bit read/write register. BAMRB specifies bits masked in the break address
specified by BARB.
Bit
31 to 0
Bit Name
BAMB31 to
BAMB0
Initial Value R/W
All 0
R/W
Note: n = 31 to 0
Description
Break Address Mask
Specifies bits masked in the channel B break
address bits specified by BARB (BAB31 to
BAB0).
0: Break address BABn of channel B is included
in the break condition
1: Break address BABn of channel B is masked
and is not included in the break condition
7.2.6 Break Data Register B (BDRB)
BDRB is a 32-bit read/write register.
Bit
31 to 0
Bit Name
BDB31 to
BDB0
Initial Value R/W
All 0
R/W
Description
Break Data Bit
Rev. 5.00 May 29, 2006 page 144 of 698
REJ09B0146-0500