SH7706 Datasheet, PDF (420/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
14.3.6 Serial Control Register (SCSCR)
The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock
output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCSCR.
Bit Bit Name Initial Value R/W Description
7
TIEs
0
R/W Transmit Interrupt Enable
Enables or disables the TXI request when the serial
transmit data is transferred from SCTDR to SCTCR and
the TDRE in SCSSR is set to 1.
0: Transmit-data-empty interrupt request (TXI) is
disabled
Note: The TXI interrupt request can be cleared by
reading TDRE after it has been set to 1, then
clearing TDRE to 0, or by clearing TIE to 0.
1: Transmit-data-empty interrupt request (TXI) is
enabled
6
RIE
0
R/W Receive Interrupt Enable
Enables or disables the receive-data-full interrupt (RXI)
request when the serial receive data is transferred from
SCRSR to SCRDR and the receive data register full bit
(RDRF) in SCSSR is set to 1. It also enables or
disables receive-error interrupt (ERI) requests.
0: Receive-data-full interrupt (RXI) and receive-error
interrupt (ERI) requests are disabled
Note: RXI and ERI interrupt requests can be cleared
by reading 1 from the RDRF flag or error flag (FER,
PER, or ORER) then clearing the flag to 0, or by
clearing RIE to 0.
1: Receive-data-full interrupt (RXI) and receive-error
interrupt (ERI) requests are enabled
Rev. 5.00 May 29, 2006 page 372 of 698
REJ09B0146-0500