SH7706 Datasheet, PDF (346/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
9.6 Examples of Use
9.6.1
Example of DMA Transfer between A/D Converter and External Memory
(Address Reload on)
In this example, DMA transfer is performed between the on-chip A/D converter (transfer source)
and the external memory (transfer destination) with address reload function on. Table 9.6 shows
the transfer conditions and register settings.
Table 9.6 Transfer Conditions and Register Settings for Transfer between On-Chip A/D
Converter and External Memory
Transfer Conditions
Transfer source: on-chip A/D converter
Transfer destination: external memory
Number of transfers: 128 (reloading 32 times)
Transfer source address: incremented
Transfer destination address: decremented
Transfer request source: A/D converter
Bus mode: burst
Transfer unit: long word
Interrupt request generated at end of transfer
Channel priority order: 0 > 2 > 3 > 1
Register
SAR_2
DAR_2
DMATCR_2
CHCR_2
Setting
H'04000080
H'00400000
H'00000080
H'00089E35
DMAOR
H'0101
When the address reload function is on, the values set in SAR_0 to SAR_3 returns to the initially
set value at each four transfers. In this example, when an interrupt request is generated from A/D
converter, longword data is read from the register in address H'04000080 in A/D converter, and it
is written to external memory address H'00400000. Since longword data has been transferred, the
values in SAR_2 and DAR_2 are H'04000084 and H'003FFFFC, respectively. The bus right is
maintained and data transfers are successively performed because this transfer is in the burst
mode.
After four transfers end, fifth and sixth transfers are performed if the address reload function is off,
and the value in SAR_2 is incremented from H'0400008C, H'04000090, H'04000094,.... If the
address reload function is on, the DMA transfer stops after the fourth transfer ends, the bus request
signal to the CPU is cleared. At this time, the value stored in SAR_2 is not incremented from
H'0400008C to H'04000090, but returns to the initially set value H'04000080. The value in
Rev. 5.00 May 29, 2006 page 298 of 698
REJ09B0146-0500