SH7706 Datasheet, PDF (63/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
Register values after a reset are shown in table 2.1.
Table 2.1 Initial Register Values
Type
Registers
Initial Value*
General registers
R0 to R15
Undefined
Control registers
SR
MD bit = 1, RB bit = 1, BL bit = 1, I3 to
I0 = 1111 (H'F), reserved bits = 0,
others undefined
GBR, SSR, SPC
Undefined
VBR
H'00000000
System registers
MACH, MACL, PR
Undefined
PC
H'A0000000
Note: * Initial value is set at power-on-reset or manual-reset.
2.1.2 General Registers
There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked
registers, with a different R0 to R7 register bank (R0_BANK0 to R7_BANK0 or R0_BANK1 to
R7_BANK1) being accessed according to the processor mode. For details, see figure 2.1.
The general register configuration is shown in figure 2.2.
31
R0^{*1 *2}
R1^*2
R2^*2
R3^*2
R4^*2
R5^*2
R6^*2
R7^*2
R8
R9
R10
R11
R12
R13
R14
R15
General Registers
0
Initialized to undefined by a reset.
Notes:
1. R0 functions as an index register in the indexed
register-indirect addressing mode and indexed
GBR-indirect addressing mode. In some instructions,
only R0 can be used as the source register or
destination register.
2. R0 to R7 are banked registers.
In privileged mode, SR.RB specifies which banked registers are
accessed as general registers (R0_BANK0 to R7_BANK0 or
R0_BANK1 to R7_BANK1).
Figure 2.2 General Registers
Rev. 5.00 May 29, 2006 page 15 of 698
REJ09B0146-0500