SH7706 Datasheet, PDF (427/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
3 PER
0
R/(W)* Parity Error
Indicates that data reception (with parity) aborted due
to a parity error in the asynchronous mode.
0: Receiving is in progress or has ended normally
[Clearing conditions]
1. The chip is reset or enters standby mode.
2. PER is read as 1, then written to with 0.
Note: Clearing the RE bit to 0 in the SCSCR does
not affect the PER bit, which retains its previous
value.
1: A receive parity error occurred
[Setting condition]
The number of 1s in receive data, including the
parity bit, does not match the even or odd parity
setting of the parity mode bit (O/E) in SCSMR.
When a parity error occurs, the SCI transfers the
receive data into the SCRDR but does not set
RDRF. Serial receiving cannot continue while PER
is set to 1. In the clock synchronous mode, serial
transmitting also cannot continue.
2 TEND
1
R
Transmit End
Indicates that when the last bit of a serial character
was transmitted, the SCTDR did not contain valid
data, so transmission has ended. TEND is a read-only
bit and cannot be written.
[Clearing condition]
TDRE is read as 1, then written to with 0.
[Setting conditions]
1. The chip is reset or enters standby mode.
2. TE bit in SCSCR is 0.
3. TDRE is 1 when the last bit of a one-byte serial
character is transmitted.
Rev. 5.00 May 29, 2006 page 379 of 698
REJ09B0146-0500