SH7706 Datasheet, PDF (336/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
1st sampling
CKIO
DREQ
DRAK
(High active)
Bus cycle
DACK
CPU
DMAC(Read)
DMAC(Write)
DMAC(Read)
DMAC(Write)
DMAC(Read)
Figure 9.23 Burst Mode, Edge Input
9.4.6 Source Address Reload Function
Channel 2 includes a reload function, in which the value returns to the value set in the SAR_2 for
each four transfers by setting the RO bit in CHCR_2 to 1. 16-byte transfer cannot be used. Figure
9.24 shows this operation. Figure 9.25 shows the timing chart of the source address reload
function, which is under the following conditions: burst mode, auto request, 16-bit transfer data
size, SAR_2 count-up, DAR_2 fixed, reload function on, and usage of only channel 2.
Transfer
request
DMAC
DMAC control
Reload control
4 time
count
RO bit = 1
Count signal
CHCR_2
DMATCR_2
Reload signal
Reload
signal
SAR_2
(initial value)
SAR_2
Figure 9.24 Source Address Reload Function Diagram
Rev. 5.00 May 29, 2006 page 288 of 698
REJ09B0146-0500