SH7706 Datasheet, PDF (106/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
3.2.3 The Translation Table Base Register (TTB)
The translation table base register (TTB) is a 32-bit register. TTB is used to store the base address
of the current page table. The contents of this register are only modified in response to a software
command. TTB is available to use by software for general purposes.
3.2.4 The TLB Exception Address Register (TEA)
The TLB exception address register (TEA) is a 32-bit register. TEA is used to store the virtual
address corresponding to a MMU or CPU address error exception after these exceptions has
occurred. This value remains valid until the next exception or interrupt occurs.
3.2.5 MMU Control Register (MMUCR)
The MMU control register (MMUCR) makes the MMU settings. Any program that modifies
MMUCR should reside in the P1 or P2 area.
Rev. 5.00 May 29, 2006 page 58 of 698
REJ09B0146-0500