SH7706 Datasheet, PDF (71/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
2.3.2 Addressing Modes
Addressing modes and effective address calculation methods are shown in table 2.2.
Table 2.2 Addressing Modes and Effective Addresses
Addressing
Mode
Register
direct
Register
indirect
Instruction
Format Effective Address Calculation Method
Rn
Effective address is register Rn. (Operand
is register Rn contents.)
@Rn
Effective address is register Rn contents.
Rn
Rn
Calculation Formula
—
Rn
Register
indirect with
post-
increment
@Rn+
Effective address is register Rn contents.
A constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
Rn + 1/2/4 ₊
1/2/4
Rn
After instruction
execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4 →
Rn
Register
indirect with
pre-
decrement
@–Rn
Effective address is register Rn contents,
decremented by a constant beforehand:
1 for a byte operand, 2 for a word operand,
4 for a longword operand.
Rn
Rn – 1/2/4 _–
Rn – 1/2/4
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4 →
Rn
(Instruction executed
with Rn after
calculation)
1/2/4
Rev. 5.00 May 29, 2006 page 23 of 698
REJ09B0146-0500