SH7706 Datasheet, PDF (629/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Sleep to Power-On Reset:
CKIO
RESETP^*1
Reset
Section 22 Power-Down Modes
STATUS
Normal^*4
Sleep^*3
*6
Reset^*3
Normal^*4
0 to 10 Bcyc^*5
0 to 30 Bcyc^*5
Notes:
1. When the PLL1’s multiplication ratio is changed by a power-on reset, keep RESETP low during the
PLL’s oscillation settling time.
2. Reset: HH (STATUS1 high, STATUS0 high)
3. Sleep: HL (STATUS1 high, STATUS0 low)
4. Normal: LL (STATUS1 low, STATUS0 low)
5. Bcyc: Bus clock cycle
6. Undefined
Figure 22.8 Sleep to Power-On Reset STATUS Output
Sleep to Manual Reset:
Reset
CKIO
RESETM^*1
STATUS Normal^*4
Sleep^*3
Reset^*2
Normal^*4
0 to 80 Bcyc^*5
Notes: 1. Keep RESETM low until STATUS becomes reset.
2. Reset: HH (STATUS1 high, STATUS0 high)
3. Sleep: HL (STATUS1 high, STATUS0 low)
4. Normal: LL (STATUS1 low, STATUS0 low)
5. Bcyc: Bus clock cycle
0 to 30 Bcyc^*5
Figure 22.9 Sleep to Manual Reset STATUS Output
Rev. 5.00 May 29, 2006 page 581 of 698
REJ09B0146-0500