SH7706 Datasheet, PDF (44/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Tables
Section 2 CPU
Table 2.1 Initial Register Values ............................................................................................ 15
Table 2.2 Addressing Modes and Effective Addresses .......................................................... 23
Table 2.3 Instruction Formats ................................................................................................ 27
Table 2.4 Classification of Instructions.................................................................................. 30
Table 2.5 Data Transfer Instructions ...................................................................................... 34
Table 2.6 Arithmetic Instructions........................................................................................... 36
Table 2.7 Logic Operation Instructions.................................................................................. 39
Table 2.8 Shift Instructions .................................................................................................... 40
Table 2.9 Branch Instructions ................................................................................................ 41
Table 2.10 System Control Instructions ................................................................................... 42
Table 2.11 Instruction Code Map............................................................................................. 46
Section 3 Memory Management Unit (MMU)
Table 3.1 Access States Designated by D, C, and PR Bits..................................................... 65
Section 4 Exception Processing
Table 4.1 Exception Event Vectors ........................................................................................ 82
Table 4.2 Exception Codes..................................................................................................... 85
Table 4.3 Types of Reset........................................................................................................ 92
Section 5 Cache
Table 5.1 LRU and Way Replacement................................................................................... 100
Table 5.2 Way to be Replaced when Cache Miss Occurs during PREF Instruction
Execution................................................................................................................ 103
Table 5.3 Way to be Replaced when Cache Miss Occurs during Execution of Instruction
Other than PREF Instruction .................................................................................. 104
Table 5.4 LRU and Way Replacement (When W2LOCK = 1) .............................................. 104
Table 5.5 LRU and Way Replacement (When W3LOCK = 1) .............................................. 104
Table 5.6 LRU and Way Replacement (When W2LOCK = 1 and W3LOCK = 1) ............... 104
Section 6 Interrupt Controller (INTC)
Table 6.1 Pin Configuration ................................................................................................... 115
Table 6.2 IRL3 to IRL0 Pins and Interrupt Levels................................................................. 117
Table 6.3 Interrupt Exception Handling Sources and Priority (IRQ Mode)........................... 119
Table 6.4 Interrupt Exception Handling Sources and Priority (IRL Mode) ........................... 121
Table 6.5 Interrupt Level and INTEVT Code ........................................................................ 123
Table 6.6 Interrupt Request Sources and IPRA to IPRE ........................................................ 124
Rev. 5.00 May 29, 2006 page xliv of xlviii