SH7706 Datasheet, PDF (468/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 14 Serial Communication Interface (SCI)
The receive margin in the asynchronous mode can therefore be expressed as in equation 1.
Equation 1:
M = 0.5 – ¹ – (L – 0.5)F – ^{D – 0.5} (1 + F) × 100%
2N
N
Where: M = Receive margin (%)
N = Ratio of clock frequency to bit rate (N = 16)
D = Clock duty cycle (D = 0 to 1.0)
L = Frame length (L = 9 to 12)
F = Absolute deviation of clock frequency
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as in equation 2.
Equation 2:
M = (0.5 – 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%.
Cautions for Clock Synchronous External Clock Mode:
• Set TE = RE = 1 only when the external clock SCK0 is 1.
• Do not set TE = RE = 1 until at least four clocks after the external clock SCK0 has changed
from 0 to 1.
• When receiving, RDRF is 1 when RE is set to zero 2.5–3.5 clocks after the rising edge of the
SCK0 input of the D7 bit in RxD0, but it cannot be copied to SCRDR.
Caution for Clock Synchronous Internal Clock Mode: In the receiving, RDRF become 1 when
RE is set to 0, 1.5 clocks after the rising edge of the SCK0 output of the D7 bit in RxD0, but it
cannot be copied to SCRDR.
Rev. 5.00 May 29, 2006 page 420 of 698
REJ09B0146-0500