SH7706 Datasheet, PDF (85/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 2 CPU
Instruction
Operation
Code
DMULS.L Rm,Rn
Signed operation of
0011nnnnmmmm1101
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
DMULU.L Rm,Rn
Unsigned operation of 0011nnnnmmmm0101
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
DT
Rn
Rn – 1 → Rn, if Rn =
0, 1 → T, else 0 → T
0100nnnn00010000
EXTS.B Rm,Rn
A byte in Rm is sign-
extended → Rn
0110nnnnmmmm1110
EXTS.W Rm,Rn
A word in Rm is sign-
extended → Rn
0110nnnnmmmm1111
EXTU.B Rm,Rn
A byte in Rm is zero-
extended → Rn
0110nnnnmmmm1100
EXTU.W Rm,Rn
A word in Rm is zero-
extended → Rn
0110nnnnmmmm1101
MAC.L
@Rm+,@Rn+
Signed operation of (Rn)
× (Rm) + MAC → MAC,
Rn + 4 → Rn,
Rm + 4 → Rm
32 × 32 + 64 → 64 bits
0000nnnnmmmm1111
MAC.W
@Rm+,@Rn+
Signed operation of (Rn)
× (Rm) + MAC → MAC,
Rn + 2 → Rn,
Rm + 2 → Rm
16 × 16 + 64 → 64 bits
0100nnnnmmmm1111
MUL.L Rm,Rn
Rn × Rm → MACL
32 × 32 → 32 bits
0000nnnnmmmm0111
MULS.W Rm,Rn
Signed operation of Rn
× Rm → MACL
16 × 16 → 32 bits
0010nnnnmmmm1111
MULU.W Rm,Rn
Unsigned operation of
Rn × Rm → MACL
16 × 16 → 32 bits
0010nnnnmmmm1110
NEG Rm,Rn
0–Rm → Rn
0110nnnnmmmm1011
NEGC Rm,Rn
0–Rm–T → Rn,
Borrow → T
0110nnnnmmmm1010
Privileged
Mode
Cycles T Bit
—
2 to (5)* —
—
2 to (5)* —
—
1
Comparison
result
—
1
—
—
1
—
—
1
—
—
1
—
—
2 to (5)* —
—
2 to (5)* —
—
2 to (5)* —
—
1 to (3)* —
—
1 to (3)* —
—
1
—
—
1
Borrow
Rev. 5.00 May 29, 2006 page 37 of 698
REJ09B0146-0500