SH7706 Datasheet, PDF (10/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Item
6.3.2 IRQ Interrupt
6.4.4 Interrupt
Request Register 0
(IRR0)
Page
116
129
Revision (See Manual for Details)
Description amended
When using edge-sensing for IRQ interrupts, clear the interrupt
source by having software read 1 from the corresponding bit in
IRR0, then write 0 to the bit. It is not necessary to clear the bit
to 0 when using level-sensing. Instead, the pin corresponding to
the interrupt request must be driven high.
Description amended
To clear one of bits IRQ5R to IRQ0R to 0, first read the bit to
confirm it is set to 1, then write 0 only to the bit to be cleared
while writing 1 to all the other bits. Only 0 can be written to bits
IRQ5R to IRQ0R.
Table amended
Bit
Bit Name Initial Value R/W Description
7, 6 —
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
5
IRQ5R 0
R/W IRQ5 Interrupt Request
Indicates whether an interrupt request is input to the
IRQ5 pin. When edge detection mode is set for IRQ5,
an interrupt request is cleared by clearing the IRQ5R
bit. It is not necessary to clear the flag when using
level-sensing, because this bit merely shows the status
of the IRQ5 pin.
0: An interrupt request is not input to IRQ5 pin
1: An interrupt request is input to IRQ5 pin
4
IRQ4R 0
R/W IRQ4 Interrupt Request
Indicates whether an interrupt request is input to the
IRQ4 pin. When edge detection mode is set for IRQ4,
an interrupt request is cleared by clearing the IRQ4R
bit. It is not necessary to clear the flag when using
level-sensing, because this bit merely shows the status
of the IRQ4 pin.
0: An interrupt request is not input to IRQ4 pin
1: An interrupt request is input to IRQ4 pin
3
IRQ3R 0
R/W IRQ3 Interrupt Request
Indicates whether an interrupt request is input to the
IRQ3 pin. When edge detection mode is set for IRQ3,
an interrupt request is cleared by clearing the IRQ3R
bit. It is not necessary to clear the flag when using
level-sensing, because this bit merely shows the status
of the IRQ3 pin.
0: An interrupt request is not input to IRQ3 pin
1: An interrupt request is input to IRQ3 pin
Rev. 5.00 May 29, 2006 page x of xlviii