SH7706 Datasheet, PDF (317/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
The DMA transfer request signals of table 9.3 are automatically withdrawn when the
corresponding DMA transfer is performed. If the cycle-steal mode is being used, they are
withdrawn at the first transfer; if the burst mode is being used, they are withdrawn at the last
transfer.
9.4.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order. Two modes (fixed mode and round-robin
mode) are selected by the priority bits PR1 and PR0 in the DMA operation register (DMAOR).
Fixed Mode: In this mode, the priority levels among the channels remain fixed. There are three
kinds of fixed modes as follows:
• CH0 > CH1 > CH2 > CH3
• CH0 > CH2 > CH3 > CH1
• CH2 > CH0 > CH1 > CH3
These are selected by the PR1 and the PR0 bits in the DMA operation register (DMAOR).
Round-Robin Mode: Each time one word, byte, or longword, or 16-byte data is transferred on
one channel, the priority order is rotated. The channel on which the transfer was just finished
rotates to the bottom of the priority order. The round-robin mode operation is shown in figure 9.3.
The priority of the round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after a reset.
Rev. 5.00 May 29, 2006 page 269 of 698
REJ09B0146-0500