SH7706 Datasheet, PDF (344/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
CMCNT Count Timing
One of four clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) obtained by dividing the peripheral clock (Pφ) can
be selected by the CKS1 and CKS0 bits of the CMCSR. Figure 9.28 shows the timing.
Peripheral clock (Pφ)
CMT clock
CMCNT0 input clock
CMCNT0
N-1
N
N+1
Figure 9.28 Count Timing
Compare Match Flag Set Timing
The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the
CMCOR register and the CMCNT counter match. The compare match signal is generated upon
the final state of the match (timing at which the CMCNT counter matching count value is
updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare
match signal will not be generated until a CMCNT counter input clock occurs. Figure 9.29 shows
the CMF bit set timing.
Rev. 5.00 May 29, 2006 page 296 of 698
REJ09B0146-0500