SH7706 Datasheet, PDF (239/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Bit*
Bit Name Initial Value R/W Description
10
A6TED2 0
R/W Area 6 Address OE/WE Assert Delay
5
A6TED1 0
4
A6TED0 0
R/W The A6TED bits specify the address to OE/WE
R/W ^{assert delay time for the PCMCIA interface}
connected to area 6.
000: 0.5-cycle delay
001: 1.5-cycle delay
010: 2.5-cycle delay
011: 3.5-cycle delay
100: 4.5-cycle delay
101: 5.5-cycle delay
110: 6.5-cycle delay
111: 7.5-cycle delay
9
A5TEH2 0
R/W Area 5 OE/WE Negate Address Delay
3
A5TEH1 0
2
A5TEH0 0
R/W The A5TEH bits specify the OE/WE negate
R/W ^{address delay time for the PCMCIA interface}
connected to area 5.
000: 0.5-cycle delay
001: 1.5-cycle delay
010: 2.5-cycle delay
011: 3.5-cycle delay
100: 4.5-cycle delay
101: 5.5-cycle delay
110: 6.5-cycle delay
111: 7.5-cycle delay
8
A6TEH2 0
R/W Area 6 OE/WE Negate Address Delay
1
A6TEH1 0
0
A6TEH0 0
R/W The A6TEH bits specify the OE/WE negate
R/W ^{address delay time for the PCMCIA interface}
connected to area 6.
000: 0.5-cycle delay
001: 1.5-cycle delay
010: 2.5-cycle delay
011: 3.5-cycle delay
100: 4.5-cycle delay
101: 5.5-cycle delay
110: 6.5-cycle delay
111: 7.5-cycle delay
Note: * The bit numbers are out of sequence.
Rev. 5.00 May 29, 2006 page 191 of 698
REJ09B0146-0500