SH7706 Datasheet, PDF (280/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Power-On Sequence
In order to use synchronous DRAM, mode setting must first be performed after powering on. To
perform synchronous DRAM initialization correctly, the bus state controller registers must first be
set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode
register setting, the address signal value at that time is latched by a combination of the RAS, CAS,
and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be
written to the synchronous DRAM mode register by performing a write to address H'FFFFD000 +
X for area 2 synchronous DRAM, and to address H'FFFFE000 + X for area 3 synchronous
DRAM. In this operation the data is ignored, but the mode write is performed as a byte-size
access. To set burst read/single write, CAS latency 1 to 3, wrap type = sequential, and burst length
1 supported by this LSI, arbitrary data is written in a byte-size access to the following addresses.
32-bit
Bus width
CAS latency 1
CAS latency 2
CAS latency 3
Area 2
FFFFD840
FFFFD880
FFFFD8C0
Area 3
FFFFE840
FFFFE880
FFFFE8C0
16-bit
Bus width
CAS latency 1
CAS latency 2
CAS latency 3
Area 2
FFFFD420
FFFFD440
FFFFD460
Area 3
FFFFE420
FFFFE440
FFFFE460
Mode register setting timing is shown in figure 8.27.
As a result of the write to address H'FFFFD000 + X or H'FFFFE000 + X, a precharge all banks
(PALL) command is first issued in the TRp1 cycle, then a mode register write command is issued
in the TMw1 cycle.
Address signals, when the mode-register write command is issued, are as follows:
32-bit
Bus width
A15 to A9
A8 to A6
A5
A4 to A2
0000100 (burst read and single write)
CAS latency
0 (burst type = sequential)
000 (burst length 1)
16-bit
Bus width
A14 to A8
A7 to A5
A4
A3 to A1
0000100 (burst read and single write)
CAS latency
0 (burst type = sequential)
000 (burst length 1)
Rev. 5.00 May 29, 2006 page 232 of 698
REJ09B0146-0500