SH7706 Datasheet, PDF (342/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 9 Direct Memory Access Controller (DMAC)
Compare Match Timer Control/Status Register (CMCSR)
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the
occurrence of compare matches, and establishes the clock used for incrementation.
Bit
Bit Name Initial Value R/W Description
15 to 8 —
All 0
R
Reserved
These bits always read as 0. The write value
should always be 0.
7
CMF
0
R/(W)* Compare match flag
This flag indicates whether CMCNT and CMCOR
values have matched or not.
0: CMCNT and CMCOR values have not matched
Clearing condition: Write 0 to CMF after
reading CMF = 1
1: CMCNT and CMCOR values have matched
6
—
0
R/W Reserved
Both read and write are available. The write value
should always be 0.
5 to 2 —
0
R
Reserved
These bits always read as 0. The write value
should always be 0.
1
CKS1
0
R/W Clock select 1 and 0
0
CKS0
0
R/W These bits select the clock input to the CMCNT
from among the four clocks obtained by dividing
the peripheral clock (Pφ). When the STR0 bit of
the CMSTR is set to 1, the CMCNT begins
incrementing with the clock selected by CKS1 and
CKS0.
00: P φ/4
01: P φ/8
10: P φ/16
11: P φ/64
Note: * The only value that can be written is 0 to clear the flag.
Rev. 5.00 May 29, 2006 page 294 of 698
REJ09B0146-0500