SH7706 Datasheet, PDF (364/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 11 Watchdog Timer (WDT)
11.2 Register Description
The WDT has two registers that select the clock, switch the timer mode, and perform other
functions. Refer to section 23, List of Registers, for more details of the addresses and access sizes.
• Watchdog timer counter (WTCNT)
• Watchdog timer control/status register (WTCSR)
11.2.1 Watchdog Timer Counter (WTCNT)
The watchdog timer counter (WTCNT) is an 8-bit read/write register that increments on the
selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an
interrupt in interval time mode. The WTCNT is initialized to H'00 only by a power-on reset
through the RESETP pin. Use a word access to write to the WTCNT, with H'5A in the upper byte.
Use a byte access to read WTCNT.
Bit
Bit Name Initial Value R/W Description
7 to 0 
All 0
R/W 8-bit counter
Note: The watchdog timer counter (WTCNT) is more difficult to write to than other registers to
prevent from the erroneous writing to the register. Refer to section 11.2.3 Notes on Register
Access.
11.2.2 Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit read/write register composed of
bits to select the clock used for the count, bits to select the timer mode, and overflow flags. The
WTCSR is initialized to H'00 only by a power-on reset through the RESETP pin. When a WDT
overflow causes an internal reset, the WTCSR retains its value. When used to count the clock
settling time for canceling a software standby, it retains its value after counter overflow. Use a
word access to write to the WTCSR, with H'A5 in the upper byte. Use a byte access to read
WTCSR.
Rev. 5.00 May 29, 2006 page 316 of 698
REJ09B0146-0500