SH7706 Datasheet, PDF (25/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

4.4.2 General Exceptions .............................................................................................. 92
4.4.3 Interrupts.............................................................................................................. 95
4.5 Usage Note........................................................................................................................ 97
Section 5 Cache.................................................................................................................... 99
5.1 Feature .............................................................................................................................. 99
5.1.1 Cache Structure.................................................................................................... 99
5.2 Register Description.......................................................................................................... 101
5.2.1 Cache Control Register (CCR) ............................................................................ 101
5.2.2 Cache Control Register 2 (CCR2)........................................................................ 102
5.3 Operation .......................................................................................................................... 105
5.3.1 Searching the Cache............................................................................................. 105
5.3.2 Read Access ......................................................................................................... 106
5.3.3 Prefetch Operation ............................................................................................... 107
5.3.4 Write Access ........................................................................................................ 107
5.3.5 Write-Back Buffer ............................................................................................... 107
5.3.6 Coherency of Cache and External Memory ......................................................... 108
5.4 Memory-Mapped Cache ................................................................................................... 108
5.4.1 Address Array ...................................................................................................... 108
5.4.2 Data Array............................................................................................................ 109
5.4.3 Usage Examples................................................................................................... 111
Section 6 Interrupt Controller (INTC)........................................................................... 113
6.1 Feature .............................................................................................................................. 113
6.2 Input/Output Pin................................................................................................................ 115
6.3 Interrupt Sources............................................................................................................... 115
6.3.1 NMI Interrupts ..................................................................................................... 115
6.3.2 IRQ Interrupt........................................................................................................ 116
6.3.3 IRL Interrupts ...................................................................................................... 117
6.3.4 On-Chip Peripheral Module Interrupts ................................................................ 118
6.3.5 Interrupt Exception Processing and Priority ........................................................ 119
6.4 Register Description.......................................................................................................... 123
6.4.1 Interrupt Priority Registers A to E (IPRA to IPRE)............................................. 124
6.4.2 Interrupt Control Register 0 (ICR0)..................................................................... 125
6.4.3 Interrupt Control Register 1 (ICR1)..................................................................... 126
6.4.4 Interrupt Request Register 0 (IRR0) .................................................................... 129
6.4.5 Interrupt Request Register 1 (IRR1) .................................................................... 131
6.4.6 Interrupt Request Register 2 (IRR2) .................................................................... 132
6.5 Operation .......................................................................................................................... 133
6.5.1 Interrupt Sequence ............................................................................................... 133
6.5.2 Multiple Interrupts ............................................................................................... 135
Rev. 5.00 May 29, 2006 page xxv of xlviii