SH7706 Datasheet, PDF(450/749 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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SH7706 Datasheet, PDF (450/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

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Section 14 Serial Communication Interface (SCI)

Figure 14.11 shows an example of SCI receive operation in the asynchronous mode.

1

Serial

data

Start

bit

Data

Parity Stop Start

bit bit bit

Data

Parity Stop

bit bit

0 D0 D1

D 7 0/1 1 0 D 0 D 1

D 7 0/1 1

1

Idling

(marking)

RDRF

FER

RXI interrupt request

generated

1 frame

Example: 8-bit data with parity and one stop bit

Reads data with

the RXI interrupt

processing routine

and clears RDRF

bit to 0

Figure 14.11 SCI Receive Operation

ERI interrupt

request generated

by framing error

14.4.2 Multiprocessor Communication

The multiprocessor communication function enables several processors to share a single serial

communication line. The processors communicate in the asynchronous mode using a format with

an additional multiprocessor bit (multiprocessor format).

In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial

communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a

data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending

cycles. The transmitting processor starts by sending the ID of the receiving processor with which it

wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor

sends transmit data with the multiprocessor bit cleared to 0.

Receiving processors skip incoming data until they receive data with the multiprocessor bit set to

1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the

data with their IDs. The receiving processor with a matching ID continues to receive further

incoming data. Processors with IDs not matching the received data skip further incoming data

until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and

receive data in this way.

Rev. 5.00 May 29, 2006 page 402 of 698

REJ09B0146-0500

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