SH7706 Datasheet, PDF (199/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 7 User Break Controller
7.2.11 Branch Source Register (BRSR)
BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer
(3 bits) which indicates the number of cycles from fetch to execution for the last executed
instruction. BRSR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0,
when BRSR is read and also initialized by power-on resets or manual resets. Other bits are not
initialized by reset. Eight BRSR registers have queue structure and a stored register is shifted
every branch.
Bit
Bit Name
31
SVF
30 to 28 PID2 to
PID0
27 to 0 BSA27 to
BSA0
Initial Value R/W
0
R
—
R
—
R
Description
BRSR Valid Flag
Indicates whether the address and the pointer by
which the branch source address can be
calculated. When a branch source address is
fetched, this flag is set to 1. This flag is cleared to
0 in reading BRSR.
0: The value of BRSR register is invalid
1: The value of BRSR register is valid
Instruction Decode Pointer
PID is a 3-bit binary pointer (0 to 7). These bits
indicate the instruction buffer number which
stores the last executed instruction before branch.
Even: PID indicates the instruction buffer number
Odd: PiD+2 indicates the instruction buffer
number
Branch Source Address
These bits store the last fetched address before
branch.
Rev. 5.00 May 29, 2006 page 151 of 698
REJ09B0146-0500