SH7706 Datasheet, PDF (626/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 22 Power-Down Modes
22.3.4 Timing of STATUS Pin Changes
The timing of STATUS1 and STATUS0 pin changes is shown in figures 22.2 through 22.9
Timing for Resets
Power-On Reset:
CKIO
RESETP
PLL settling
time
STATUS
Normal*²
Reset^*1
0 to 5 Bcyc^*3
Notes: 1. Reset: HH (STATUS1 high, STATUS0 high)
2. Normal: LL (STATUS1 low, STATUS0 low)
3. Bcyc: Bus clock cycle
0 to 30 Bcyc^*3
Figure 22.2 Power-On Reset STATUS Output
Manual Reset:
Normal^*2
CKIO
RESETM^*1
STATUS
Normal^*3
Reset^*2
Normal^*3
0 Bcyc or more^*4
0 to 30 Bcyc^*4
Notes:
1. During manual reset, STATUS becomes HH (reset) and the internal reset begins after waiting for the
executing bus cycle to end.
2. Reset: HH (STATUS1 high, STATUS0 high)
3. Normal: LL (STATUS1 low, STATUS0 low)
4. Bcyc: Bus clock cycle
Figure 22.3 Manual Reset STATUS Output
Rev. 5.00 May 29, 2006 page 578 of 698
REJ09B0146-0500