SH7706 Datasheet, PDF (170/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
Interrupt Source
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
IPR (Bit
(Initial Value) Numbers)
Priority
within IPR Default
Setting Unit Priority
TMU0 TUNI0
H'400 (H'400)
0 to 15 (0) IPRA (15 to 12) —
High
TMU1 TUNI1
H'420 (H'420)
0 to 15 (0) IPRA (11 to 8) —
TMU2 TUNI2
H'440 (H'440)
0 to 15 (0) IPRA (7 to 4) High
TICPI2
H'460 (H'460)
Low
RTC ATI
H'480 (H'480)
0 to 15 (0) IPRA (3 to 0) High
PRI
H'4A0 (H'4A0)
CUI
H'4C0 (H'4C0)
Low
SCI
ERI
(SCI0) _RXI
H'4E0 (H'4E0)
H'500 (H'500)
0 to 15 (0) IPRB (7 to 4) High
TXI
H'520 (H'520)
TEI
H'540 (H'540)
Low
WDT ITI
H'560 (H'560)
0 to 15 (0) IPRB (15 to 12) —
BSC RCMI
H'580 (H'580)
0 to 15 (0) IPRB (11 to 8) High
(REF) ROVI
H'5A0 (H'5A0)
Low
Low
Note: * The code corresponding to an interrupt level shown in table 6.5 is set.
Rev. 5.00 May 29, 2006 page 122 of 698
REJ09B0146-0500