SH7706 Datasheet, PDF (224/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 8 Bus State Controller (BSC)
Bit Bit Name Initial Value R/W Description
4
DRAMTP2 0
R/W Area 2, Area 3 Memory Type
3
DRAMTP1 0
2
DRAMTP0 0
R/W Designate the types of memory connected to physical
R/W ^{space areas 2 and 3. Ordinary memory, such as ROM,}
SRAM, or flash ROM, can be directly connected.
Synchronous DRAM can also be directly connected.
000: Areas 2 and 3 are ordinary memory
001: Reserved (Setting prohibited)
010: Area 2: ordinary memory; area 3: synchronous
DRAM^*3
011: Areas 2 and 3 are synchronous DRAM^{*2 *3}
100: Reserved (Setting prohibited)
101: Reserved (Setting prohibited)
110: Reserved (Setting prohibited)
111: Reserved (Setting prohibited)
1
A5PCM
0
R/W Area 5 Bus Type
Designates whether to access physical space area 5
as PCMCIA space.
0: Access physical space area 5 as ordinary memory
1: Access physical space area 5 as PCMCIA space
0
A6PCM
0
R/W Area 6 Bus Type
Designates whether to access physical space area 6
as PCMCIA space.
0: Access physical space area 6 as ordinary memory
1: Access physical space area 6 as PCMCIA space
Notes: 1. Samples the value of the external pin (MD5) designating endian at power-on reset.
2. When selecting this mode, set the same bus width for areas 2 and 3.
3. Do not access to the SRAM when the clock ratio is I φ : B φ = 1:1.
Rev. 5.00 May 29, 2006 page 176 of 698
REJ09B0146-0500