SH7706 Datasheet, PDF (182/749 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series

Section 6 Interrupt Controller (INTC)
source flag after it has been cleared, then wait for the interval shown in "Time for
priority decision and SR mask bit comparison" in table 6.7 before clearing the BL bit
or executing an RTE instruction.
Program
execution state
Yes
ICR1.MAI = 1?
No
No
NMI = low?
Yes
Interrupt
No
generated?
No
ICR1.BLMSK = 1?
Yes
NMI?
No
Yes
Yes
No
NMI?
Yes
SR. BL= 0 or
sleepmode?
Yes
No
Level 15
No
interrupt?
IRQOUT = 1?
Set interrupt cause in
INTEVT, INTEVT2
Save SR to SSR;
save PC to SPC
Set BL/MD/RB
bits in SR to 1
Yes
Level 14
No
interrupt?
Yes
I3 to I0 level
14 or lower?
Yes
Level 1
No
interrupt?
No
Yes
I3 to I0 level
13 or lower?
Yes
No
Yes
I3 to I0
level 0?
No
Branch to exception
handler
I3 to I0: Interrupt mask bits in status register (SR)
Figure 6.3 Interrupt Operation Flowchart
Rev. 5.00 May 29, 2006 page 134 of 698
REJ09B0146-0500