SH7080_09 Datasheet, PDF (990/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
SCL
(Master output)
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
RDRF
9
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A
A
ICDRS
Data 1
Data 2
ICDRR
User
processing
Data 1
[3] Set ACKBT [3] Read ICDRR [4] Read ICDRR
Figure 18.12 Slave Receive Mode Operation Timing (2)
18.4.6 Clock Synchronous Serial Format
This module can be operated with the clock synchronous serial format, by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
(1) Data Transfer Format
Figure 18.13 shows the clock synchronous serial transfer format.
The transfer data is output from the fall to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the
SDAO bit in ICCR2.
SCL
SDA
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Figure 18.13 Clock Synchronous Serial Transfer Format
Rev. 4.00 Dec. 15, 2009 Page 930 of 1558
REJ09B0181-0400