SH7080_09 Datasheet, PDF (1385/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 25 RAM
Section 25 RAM
This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a
32-bit data bus (L bus), and to the direct memory access controller (DMAC), and data transfer
controller (DTC) by a 32-bit data bus (I bus), enabling 8, 16, or 32-bit width access to data in the
on-chip RAM.
The on-chip RAM is allocated to different addresses according to each product as shown in figure
25.1, and the on-chip RAM is divided into page 0 and page 1 based on the addresses. The on-chip
RAM can be accessed from the CPU (via the L bus) and the DMAC/DTC (via the I bus). When
different buses request to access the same page simultaneously, the priority becomes I bus
(DMAC/DTC) > L bus (CPU). Since such kind of conflict degrades the RAM access performance,
software should be created so as to avoid conflicts. For example, conflict does not occur when the
buses access different pages. An access from the L bus (CPU) is a 1-cycle access as long as page
conflict does not occur. The number of bus cycles in accesses from the I bus (DMAC/DTC) differ
depending on the ratio between the internal clock (Iφ) and bus clock (Bφ), and the operating state
of the DMAC/DTC. The contents of the on-chip RAM are retained in sleep mode or software
standby mode, and at a power-on reset or manual reset. However, the contents of the on-chip
RAM are not retained in deep software standby mode.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the RAM control
register (RAMCR). For details on the RAM control register (RAMCR), refer to section 26.3.7,
RAM Control Register (RAMCR).
H'FFFF4000
H'FFFF8000
H'FFFF9FFF
Page 0
8 kbytes
H'FFFFA000
H'FFFFBFFF
Page 1
8 kbytes
SH7083/SH7084/SH7085
(256-kbyte flash memory version)
(16 kbytes)
Page 0
24 kbytes
H'FFFF9FFF
H'FFFFA000
H'FFFFBFFF
Page 1
8 kbytes
SH7083/SH7084/SH7085
(512-kbyte flash memory version)/
SH7086
(32 kbytes)
Figure 25.1 On-chip RAM Addresses
RAM0200A_010020030800
Rev. 4.00 Dec. 15, 2009 Page 1325 of 1558
REJ09B0181-0400