SH7080_09 Datasheet, PDF (530/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.6 Timer Status Register (TSR)
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The
MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5.
• TSR_0, TSR_1, TSR_2, TSR_3, TSR_4
Bit: 7
TCFD
Initial value: 1
R/W: R
6
5
4
3
2
1
0
- TCFU TCFV TGFD TGFC TGFB TGFA
1
0
0
0
0
0
0
R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Bit
Bit Name Value R/W Description
7
TCFD
1
R
Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1 to 4.
In channel 0, bit 7 is reserved. It is always read as 1 and
the write value should always be 1.
0: TCNT counts down
1: TCNT counts up
6
—
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
5
TCFU
0
R/(W)*¹ Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1 and 2 are set to phase
counting mode. Only 0 can be written, for flag clearing.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0 and the write value should always be 0.
[Setting condition]
• When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
• When 0 is written to TCFU after reading TCFU = 1*²
Rev. 4.00 Dec. 15, 2009 Page 470 of 1558
REJ09B0181-0400