SH7080_09 Datasheet, PDF (361/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.6 SDRAM Interface
SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has
11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin
for setting precharge mode in read and write command cycles.
The control signals for direct connection of SDRAM are RASU, RASL, CASU, CASL, RDWR,
DQMUU, DQMLU, DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and CS3 are
common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted. SDRAM
can be connected to up to 2 spaces. The data bus width of the area that is connected to SDRAM
can be set to 32 or 16 bits.
Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as
SDRAM operating mode.
Commands for SDRAM can be specified by RASU, RASL, CASU, CASL, RDWR, and specific
address signals. These commands are shown below.
• NOP
• Auto-refresh (REF)
• Self-refresh (SELF)
• All banks precharge (PALL)
• Specified bank precharge (PRE)
• Bank active (ACTV)
• Read (READ)
• Read with precharge (READA)
• Write (WRIT)
• Write with precharge (WRITA)
• Write mode register (MRS)
The byte to be accessed is specified by DQMUU, DQMUL, DQMLU and DQMLL. Reading or
writing is performed for a byte whose corresponding DQMxx low. For details on the relationship
between DQMxx and the byte to be accessed, refer to section 9.5.1, Endian/Access Size and Data
Alignment.
Figures 9.14 to 9.16 show shows an example of the connection of SDRAM with the LSI.
Rev. 4.00 Dec. 15, 2009 Page 301 of 1558
REJ09B0181-0400