SH7080_09 Datasheet, PDF (588/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT value
H'0F07
H'09FB
H'0532
H'0000
TIOCA
Time
TGRA
H'0532
H'0F07
H'09FB
TGRC
H'0532
H'0F07
Figure 11.18 Example of Buffer Operation (2)
Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer
Operation: The timing for transfer from buffer registers to timer general registers can be selected
in PWM mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer
operation transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match
(initial setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as
transfer timing is one of the following cases.
• When TCNT overflows (H'FFFF to H'0000)
• When H'0000 is written to TCNT during counting
• When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits
in TCR
Note: TBTM must be modified only while TCNT stops.
Figure 11.19 shows an operation example in which PWM mode 1 is designated for channel 0 and
buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are
TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare
match B. The TTSA bit in TBTM_0 is set to 1.
Rev. 4.00 Dec. 15, 2009 Page 528 of 1558
REJ09B0181-0400