SH7080_09 Datasheet, PDF (51/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Table 9.3
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Table 9.6
Table 9.7
Table 9.8
Table 9.9
Table 9.10
Table 9.11
Table 9.12
Table 9.13
Table 9.14
Table 9.15
Table 9.16
Table 9.17
Table 9.18
Table 9.19
Table 9.20
Table 9.20
Table 9.21
Table 9.21
Table 9.22
Table 9.23
Address Map: SH7083 (256-Kbyte Flash Memory Version)
in On-Chip ROM-Disabled Mode........................................................................... 223
Address Map: SH7083 (512-Kbyte Flash Memory Version)
in On-Chip ROM-Enabled Mode ............................................................................ 224
Address Map: SH7083 (512-Kbyte Flash Memory Version)
in On-Chip ROM-Disabled Mode........................................................................... 225
Address Map: SH7084 (256-Kbyte Flash Memory Version)
in On-Chip ROM-Enabled Mode ............................................................................ 226
Address Map: SH7084 (256-Kbyte Flash Memory Version)
in On-Chip ROM-Disabled Mode........................................................................... 228
Address Map: SH7084 (512-Kbyte Flash Memory Version)
in On-Chip ROM-Enabled Mode ............................................................................ 229
Address Map: SH7084 (512-Kbyte Flash Memory Version)
in On-Chip ROM-Disabled Mode........................................................................... 230
Address Map: SH7085 (256-Kbyte Flash Memory Version)
in On-Chip ROM-Enabled Mode ............................................................................ 232
Address Map: SH7085 (256-Kbyte Flash Memory Version)
in On-Chip ROM-Disabled Mode........................................................................... 233
Address Map: SH7085 (512-Kbyte Flash Memory Version)
in On-Chip ROM-Enabled Mode ............................................................................ 234
Address Map: SH7085 (512-Kbyte Flash Memory Version)
in On-Chip ROM-Disabled Mode........................................................................... 236
Address Map: SH7086 in On-Chip ROM-Enabled Mode....................................... 237
Address Map: SH7086 in On-Chip ROM-Disabled Mode...................................... 239
Register Configuration ............................................................................................ 241
32-Bit External Device Access and Data Alignment .............................................. 285
16-Bit External Device Access and Data Alignment .............................................. 286
8-Bit External Device Access and Data Alignment ................................................ 287
Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (1)-1 ........................... 306
Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (1)-2 ........................... 307
Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (2)-1 ........................... 308
Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (2)-2 ........................... 309
Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (3)............................... 310
Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (4)-1 ........................... 311
Rev. 4.00 Dec. 15, 2009 Page xlix of lviii
REJ09B0181-0400