SH7080_09 Datasheet, PDF (319/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1, 0
HW[1:0] 00
R/W Delay Cycles from RD and WRxx Negation to Address
and CSn Negation
Specify the number of delay cycles from RD and WRxx
negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
(4) SDRAM
When SDRAM is selected in areas 2 and 3, the WTRP1/0, WTRCD0/1, TRWL1/0, and WTRC1/0
bit settings are effective in both areas in common. When SDRAM should be connected to only one
area, select area 3 for SDRAM connection. In this case, the normal space or SRAM with byte
selection must be selected for area 2.
• CS2WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
A2CL[1:0]
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R/W R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 11 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
10
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
Rev. 4.00 Dec. 15, 2009 Page 259 of 1558
REJ09B0181-0400