SH7080_09 Datasheet, PDF (326/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Bit
3 to 0
Bit Name
TEH[3:0]
Initial
Value
0000
R/W Description
R/W Delay Cycles from RD and WE Negation to Address
Specify the number of address hold cycles from RD and
WEn negation in PCMCIA interface.
0000: 0.5 cycle
0001: 1.5 cycles
0010: 2.5 cycles
0011: 3.5 cycles
0100: 4.5 cycle
0101: 5.5 cycles
0110: 6.5 cycles
0111: 7.5 cycles
1000: 8.5 cycle
1001: 9.5 cycles
1010: 10.5 cycles
1011: 11.5 cycles
1100: 12.5 cycle
1101: 13.5 cycles
1110: 14.5 cycles
1111: 15.5 cycles
Rev. 4.00 Dec. 15, 2009 Page 266 of 1558
REJ09B0181-0400