SH7080_09 Datasheet, PDF (1601/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Item
Page
10.5.3 Module Standby 421
Mode Setting
10.5.10 Notes on Using 423 to
Peripheral Module
425
Request Modes
11.4.8 Complementary 589
PWM Mode
Figure 11.77 Example of
Operation when Buffer
Transfer is Linked with
Interrupt Skipping (BTE1
= 1 and BTE0 = 0)
Figure 11.78
590
Relationship between Bits
T3AEN and T4VEN in
Timer Interrupt Skipping
Set Register (TITCR) and
Buffer Transfer-Enabled
Period
15.3.8 Serial Port
740
Register (SCSPTR)
Revision (See Manual for Details)
Description amended
Note that software standby mode or module standby mode
must not be entered while the DMAC is operating. Before
entering software standby mode or module standby mode,
return the channel control registers (CHCR_0 to CHCR_3)
and DMA operation register (DMAOR) to their initial values.
Newly added
Figure replaced
Figure replaced
Table amended
Bit: 7
6
5
4
3
2
1
0
EIO
-
-
-
SPB1IO SPB1DT SPB0IO SPB0DT
Initial value: 0
0
0
0
0
-
0
1
R/W: R/W -
-
- R/W R/W R/W R/W
Initial
Bit
Bit Name value
R/W Description
7
EIO
0
R/W Error Interrupt Only
Enables or disables RXI interrupts. While the EIO bit is
set to 1, the SCI does not request an RXI interrupt to
the CPU even if the RIE bit is set to 1.
0: The RIE bit enables or disables RXI and ERI
interrupts. While the RIE bit is 1, RXI and ERI
interrupts are sent to the INTC.
Rev. 4.00 Dec. 15, 2009 Page 1541 of 1558
REJ09B0181-0400