SH7080_09 Datasheet, PDF (958/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
17.5 SSU Interrupt Sources and DTC
The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,
transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive
data register full, and a transmit data register empty can activate the DTC for data transfer.
Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector
address, and both a transmit data register empty and a transmit end interrupts are allocated to the
SSTXI vector address, the interrupt source should be decided by their flags. Table 17.8 lists the
interrupt sources.
When an interrupt condition shown in table 17.8 is satisfied, an interrupt is requested. Clear the
interrupt source by CPU or DTC data transfer.
Table 17.8 SSU Interrupt Sources
Abbreviation Interrupt Source
Symbol Interrupt Condition DTC Activation
SSERI
Overrun error
SSOEI (RIE = 1) • (ORER = 1) ⎯
Conflict error
SSCEI (CEIE = 1) • (CE = 1) ⎯
SSRXI
Receive data register full SSRXI (RIE = 1) • (RDRF = 1) Yes
SSTXI
Transmit data register empty SSTXI (TIE = 1) • (TDRE = 1) Yes
Transmit end
SSTEI (TEIE = 1) • (TEND = 1) ⎯
Rev. 4.00 Dec. 15, 2009 Page 898 of 1558
REJ09B0181-0400